There are different instruction-set architectures in the field of computer. Object codes of operation system and application programs compiled for one instruction set architecture may be unable to be executed on a computer based on a different instruction set architecture.
The full system simulator (termed as simulator in the following) runs on a computer (termed as host in the following) based on an instruction set architecture, but can simulate a computer (termed as guest in the following) based on a different instruction set architecture. By means of the simulator, the object codes of operation system and application programs compiled for the guest can be executed on the host, as if they are directly executed on the guest.
Computer software usually accesses memory data based on logical addresses. When the computer executes an instruction accessing the memory, the memory access is finally performed by converting the logical address to the physical address through a memory management unit (MMU). When the software is to be executed, a page table for defining a map from the logical address space to the physical address space is established. Entries of the page table are buffered through a translation look-aside buffer (TLB) to increase the speed. In the following, the address as mentioned refers to that for data access unless specifically pointed out.
To increase the processing speed, the simulator usually adopts the dynamic binary translation technique to translate the guest software into a code sequence based on the host instruction set architecture (called as translated code in the following). In performing the binary translation, the simulator is required to simulate the processing of the MMU in the guest to translate the logical addresses of the guest program to the guest physical addresses (i.e., host logical addresses). When the host executes the translated code, the MMU of the host translates the translated guest physical addresses to host physical addresses.
When the simulator executes the guest program, it is required to translate the guest logical addresses into the guest physical addresses in the process of binary translation. This process greatly reduces the execution efficiency of the simulator.